1. Field of the Invention
The present invention is directed to a method for producing a metallization level having interconnects and contacts connecting the interconnects to a substrate.
2. Description of the Prior Art
Wiring with ongoing miniaturization is increasingly gaining in significance for the reliability and the performance of integrated circuits. Given miniaturization of the gate length, MOS transistors enable higher saturation currents. The maximally allowable current through a contact or through an interconnect, however, becomes smaller given miniaturization of the cross section thereof.
Problems in the wiring arise particularly due to Joule effect in conductor regions having high resistance given high current densities. In interaction with electromigration, the wiring can even be completely destroyed (see, for example, L. A. Miller, et al., VMIC 1992 Conf. Proc. 398, IEEE Catalog No. 92ISMIC-101, J. Tao et at., VMIC 1991 Conf. Proc. 390, IEEE Catalog No. 91TH0359-0). In order to avoid this, particular care must be exercised to avoid high and non-uniform electrical resistances in a wiring process that should be suitable for dimensions in the 0.25 .mu.m range because of the high current densities that occur therein.
Numerous methods for manufacturing wiring or metallization levels are known from the literature. A metallization level has conductor runs forming interconnects on an insulating layer which physically separate the conductor runs (interconnects) from the substrate. The conductor runs can be electrically connected to the substrate by means of filled contact holes in the insulating layer to form contacts.
U. Fritsch et al., VMIC 1988, Conf. Proc. 21, IEEE Catalog No. 88CH2624-5 discloses that a planarizing SiO.sub.2 layer be applied on a substrate surface that has gate electrodes. Contact holes are opened in the SiO.sub.2 layer. A thin Ti/TiN layer is sputtered thereon surface-wide and the contact holes are filled with tungsten. Interconnects are produced thereon by surface-wide sputtering of an aluminum layer that contains silicon and titanium and by structuring the AlSiTi and Ti/TiN layers. Subsequently, an oxide layer that is planarized is applied surface-wide. A boundary surface of materials arises in this process between the contact hole fill and the interconnect, which leads to a transition or contact resistance.
Uttecht et at., VMIC 1991 Conf. Proc. 20, IEEE Catalog No. 91TH0359-0 discloses a method for producing wiring levels wherein the contacts are produced independently of the interconnects. The contacts are formed of tungsten and the interconnects are formed of an aluminum alloy. For increasing the packing density, it is permitted in this method that the interconnect only partially cover the contacts. Alignment imprecisions in the manufacture of the interconnect thus act directly on the cross section of the boundary surface between contact and interconnect. Over and above this, transition or contact resistances are formed at this boundary surface.
C. W. Kaanta et al., VMIC 1991 Conf. Proc. 144, IEEE Catalog No. 91TH0359-0 discloses a method for manufacturing a wiring level wherein both the contacts as well as the interconnects are produced in one process step by deposition of tungsten. A boundary surface between the contacts and the interconnects is thereby avoided. The interconnects are subsequently formed by structuring the tungsten layer located at the surface. In this structuring, an alignment imprecision leads to a reduction of the filled contact cross section.
J. L. Yeh et al., VMIC 1988 Conf. Proc. 95, IEEE Catalog No. 88CH2624-5 discloses a method wherein, given employment of an etching stop layer and of two photolithography steps, an opening that represents the negative of the contacts and of the interconnects is produced in a dielectric layer. The contacts and the interconnects are formed by filling this opening with metal. A boundary surface between contact and interconnect is thereby avoided. The overlap between contact and interconnect amounts to 100% as a result of self-alignment. The structural fineness, however, is limited by self-alignment edges of the masks. Alignment imprecisions in this process lead to constriction of the contacts and size reduction of the transition area between interconnect and contact.
Further, the reference of Yeh et al., VMIC 1988 Conf. Proc. 95, IEEE Catalog No. 88CH2624-5 discloses another method for producing a wiring level. Trenches that have the course of the interconnects are thereby etched in a dielectric layer that is provided with an etch stop. These trenches are filled up by a conformally deposited metal layer. The trenches are widened at locations at which contacts are to be formed, so that the conformally deposited metal layer does not completely fill up the trenches at these locations. During the anisotropic re-etching of the metal layer, the bottom surfaces of the trenches are exposed in the widened regions and spacers arise at the walls of the trenches. These spacers are used as a self-aligned etching mask for producing a contact hole by removing the dielectric layer at the floor of the trench. Subsequently, the contact holes are filled with metal. In this method, the packing density cannot be arbitrarily reduced, since a widening of the interconnects is required for producing the contacts.
S. Roehl et al., VMIC 1992 Conf. Proc. 22, IEEE Catalog No. 92ISMIC-101 discloses a method for producing a wiring level wherein the contacts and the interconnects are separately produced. As a result thereof, a boundary surface that leads to a transition or contact resistance is formed. In this method, imprecisions in alignment directly influence the overlap between interconnect and contact.
C. W. Kaanta et al., VMIC 1991 Conf. Proc. 144, IEEE Catalog No. 91TH0359-0 discloses a method for producing a wiring level wherein a dielectric layer is applied onto a planar substrate surface, a contact hole mask being formed on this dielectric layer and an interconnect mask being formed on this contact hole mask. By step-by-step, selective etching, the contact holes are etched first and, after the structure of the interconnect mask has been transferred into the contact hole mask in a further etching step, the interconnects are then etched. Finally, contacts and interconnects are filled by metal deposition. Overlap between contact and interconnect is assured in this method on the basis of self-alignment. Imprecisions in alignment in this method, however, lead to a constriction of the contacts and to a reduction in size of the transition area between interconnect and contact.
U.S. Pat. No. 4,789,648 discloses a method for producing a wiring level wherein an etch stop mask at the surface of a dielectric layer is structured with the assistance of a contact hole mask. Subsequently, another dielectric layer is deposited surface-wide. The upper dielectric layer is structured with the assistance of an interconnect mask. Exposed parts of the lower dielectric layer are thereby also etched away. Due to the etching stop layer, the interconnect pattern is transferred only into the upper dielectric layer. Subsequently, contacts and interconnects are finished by being filled with metal. The arrangement of the interconnects relative to the contacts ensues self-aligned. Imprecisions in alignment, however, lead to the fact that the contacts are constricted and the transition area between interconnect and contact is reduced in size.